Method and device for forming an STI type isolation in a semiconductor device

ABSTRACT

A trench isolation in a semiconductor device, and a method for fabricating the same, includes: forming a trench having inner sidewalls for device isolation in a silicon substrate; forming an oxide layer on a surface of the silicon substrate that forms the inner sidewalls of the trench; supplying healing elements to the silicon substrate to remove dangling bonds; and filling the trench with a device isolation layer, thereby forming the trench isolation without dangling bonds causing electrical charge traps.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a Shallow Trench Isolation (STI)type semiconductor device and a method for manufacturing an STI typesemiconductor device. More particularly, the present invention relatesto a method for manufacturing an STI type semiconductor device whereinthe interface between a silicon substrate and a device isolation layerhas enhanced electrical characteristics so that a leakage current may bereduced.

[0003] 2. Description of the Related Art

[0004] As is well known in the art, a dynamic random access memory(DRAM) having a memory cell comprising a transistor and a capacitor maybe downsized to produce a higher degree of integration in the DRAM.

[0005] Accordingly, as device dimensions of the memory cell are reduced,the dimensions of active regions and the space therebetween are reducedas well. Also, isolation regions, which play an important role inpreventing current leakage between two adjacent devices, become narrow.High integration of the devices may cause several problems. For example,during formation of a field oxide layer, a bird's beak may occur at theedge of the active region allowing current leakage in a gate oxidelayer.

[0006] A conventional trench isolation structure has been proposed toovercome the above-mentioned problems and is widely used in highlyintegrated semiconductor memory devices. The conventional trenchisolation structure includes a trench region formed in a siliconsubstrate on which a well region is formed with a depth sufficient forisolating adjacent devices. A trench area is etched using a trenchetching mask, which is formed by the patterning of a pad oxide and asilicon nitride which were deposited over the silicon substrate.

[0007] The etch process comprises the steps of forming a pad oxide and anitride layer on a silicon substrate, selectively etching the pad oxideand the nitride layer, and dry etching the silicon substrate by usingthe patterned pad oxide and nitride layer as an etching mask.

[0008] Continuing, the trench area in the silicon substrate on which awell region was formed is anisotropically etched. Usually, the siliconsubstrate, which was exposed by the anisotropic etching process, hasmany crystal defects caused by the anisotropic dry etching process. Athermal process, such as annealing, follows to heal these crystaldefects. Therefore, a thermal oxide is formed on the silicon substrate,but many crystal defects may still exist between the thermal oxide layerand the silicon substrate. Defects in the silicon substrate move easilyso that the morphology of the trench sidewall deteriorates anddislocations occur easily. Additionally, dangling bonds that exist inthe crystal defect become trap sites of electrical charges, therebycausing a leakage current during memory cell device operation.

SUMMARY OF THE INVENTION

[0009] It is therefore a feature of an embodiment of the presentinvention to provide an STI type semiconductor device and a method formanufacturing an STI type semiconductor device with enhanced devicecharacteristics, whereby a leakage current during device operation and acharge leak from a capacitor may be reduced.

[0010] In accordance with one feature of an embodiment of the presentinvention, there is provided a method for manufacturing a trenchisolation, the method comprising: forming a trench for device isolationon a silicon substrate, wherein the trench has inner sidewalls; formingan oxide layer on a surface of the silicon substrate that forms theinner sidewalls of the trench; supplying healing elements to the siliconsubstrate to remove dangling bonds; and filling the trench with a deviceisolation layer, thereby forming the trench isolation without danglingbonds trapping electrical charges.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other features and advantages of the presentinvention will become apparent from the following description of thepreferred embodiments given in conjunction with the accompanyingdrawings, in which:

[0012] FIGS. 1-5 are cross-sectional views of a semiconductor deviceshowing manufacturing steps for forming a trench isolation in accordancewith an embodiment of the present invention; and

[0013] FIGS. 6-7 are cross-sectional views of a semiconductor devicehaving a trench isolation structure in accordance with anotherembodiment of the present invention, wherein FIGS. 6-7 showmanufacturing processes that replace the manufacturing process shown inFIG. 3.

DETAILED DESCRIPTION OF THE INVENTION

[0014] This application relies for priority upon Korean PatentApplication No. 2001-52396, filed on Aug. 29, 2001, and entitled: “AMethod and Device for Forming an STI Type Isolation in a SemiconductorDevice” the contents of which are incorporated herein by reference intheir entirety.

[0015] A method for forming an STI type semiconductor device having alow level of dangling bonds and a low level of defects between an oxidelayer and a silicon substrate in a trench region includes: forming atrench area in the silicon substrate, forming an oxide layer on thetrench area in the silicon substrate, supplying healing elements to thetrench area in the silicon substrate and filling the trench area with adevice isolation layer.

[0016] The healing elements supplied to the trench area in the siliconsubstrate are preferably fluorine. The healing elements may be suppliedbefore, after or simultaneously with the step of forming an oxide layerin the trench region. For example, fluorine may be contained in theoxide layer if a thermal process, which forms a thermal oxide layer inthe trench region, is carried out in an oxygen and fluorine gasatmosphere. Thereby, fluorine gas is supplied directly through theinterface boundary of the thermal oxide layer and the silicon substratein the trench region.

[0017] Healing elements may be supplied after the formation of an oxidelayer in a trench region by annealing in a fluorine gas atmosphere.Also, healing elements may be supplied by forming an ion implantinglayer such as a polysilicon layer on the oxide layer in the trenchregion, implanting healing elements in the ion implanting layer throughan ion implantation, and diffusing healing elements through the oxidelayer to the interface boundary of the silicon substrate of the trenchregion and the oxide layer.

[0018] An STI type semiconductor device exhibiting the features of thepresent invention comprises a silicon substrate having a trench formedthereon, a filling layer positioned in the trench for device isolation,and a silicon oxide layer containing healing elements positioned betweenthe filling layer and the silicon substrate. The STI type semiconductordevice may further comprise a barrier layer positioned between thesilicon oxide layer and the filling layer.

[0019] In a device according to an embodiment of the present invention,diffused healing elements are preferably contained in the interfaceboundary, which is an adjacent region between the silicon oxide layerand the silicon substrate. A silicon nitride layer capable of preventingthe diffusion of oxygen and other elements may be used to form thebarrier layer. A chemical vapor deposition (CVD) silicon oxide layer ora spin on glass (SOG) layer may be used as the filling layer forisolation in the STI type semiconductor device.

Embodiment 1

[0020]FIG. 1-FIG. 5 show cross-sectional views of a semiconductor devicesetting forth stages in a manufacturing process for forming a trenchisolation in accordance with an embodiment of the present invention.FIG. 1 shows a trench etching mask (16) which is made of a pad oxidelayer (12) and silicon nitride layer (14) on a silicon substrate (10).Specifically, the pad oxide layer (12) is formed on the siliconsubstrate (10) and the silicon nitride layer (14), which acts as anetching prevention or barrier layer, is deposited by CVD. A photoresistpattern for a trench is formed by a photolithography process. Thesilicon nitride layer (14) and pad oxide layer (12) are etched throughand the photoresist pattern is removed, thereby forming the trenchetching mask (16).

[0021]FIG. 2 shows an etching of a silicon substrate (10) using thetrench etching mask (16) thereby forming a trench (21) in the siliconsubstrate. Preferably, etching the silicon substrate is accomplished byan anisotropic etch, and sloped sidewalls are formed inside the trench(21) while etching the silicon substrate.

[0022]FIG. 3 shows thermally oxidizing the sidewall inside the trench(21) to form a sidewall thermal oxide layer (not shown) inside thetrench. A furnace or a rapid thermal process machine at approximately700° C. may be used to perform this thermal oxidation. Simultaneously,fluorine gas or NF₃ containing fluorine is supplied during the thermaloxidation in order to allow the sidewall thermal oxide layer (23) andthe silicon substrate inside the trench to contain fluorine therein.

[0023]FIG. 4 shows a silicon nitride liner (25) formed on the entiresilicon substrate. The silicon nitride liner (25) is preferablydeposited by CVD. Generally, the silicon nitride liner is deposited to athickness of approximately 100 Angstroms. A device isolation layer (27)is formed on the silicon nitride liner (25) to fill the trench. Thedevice isolation layer (27) is preferably a silicon oxide layer, and ispreferably deposited by CVD. If an aspect ratio of the gap to be filledis high, a high-density-plasma (HDP) CVD method, which has good stepcoverage, may be used to deposit the device isolation layer (27).Alternatively, a SOG oxide may be used.

[0024] Referring to FIG. 4 and FIG. 5, a chemical mechanical polishingis performed to remove the device isolation layer (27) outside of thetrench area and expose the trench etching mask. Silicon nitride layer(14), which forms part of the trench etching mask (16), is removed by awet etching process; preferably, a phosphoric acid wet etching process.The pad oxide layer (12) is removed to form a trench device isolationlayer (29). Preferably, the trench device isolation layer (29) has abouta same level of surface height as the substrate (10). It should benoted, however, that formation of the trench is not limited to themethod described herein, and the trench may be formed using any othermethod that is known in the art.

[0025] In this embodiment, fluorine gas is supplied to the interfaceboundary between the trench device isolation layer (29) and thesubstrate (10) and removes dangling bonds therebetween. Therefore, acharge leak associated with operating a silicon device and an electricalcharge leak associated with a storage node, caused by dangling bondsthat trap charges, may be prevented.

Embodiment 2

[0026] The process of embodiment 2 is similar to that of embodiment 1,with the exception of the method of supplying fluorine gas. Unlikeembodiment 1, fluorine gas is not supplied to the interface between thetrench device isolation layer (29) and the substrate (10) during thermaloxidation of the trench sidewall. In embodiment 2, the simultaneousprocesses shown in FIG. 3 of embodiment 1, including both thermaloxidation and supplication of fluorine gas or NF₃ containing fluorine,are divided into two steps, as shown in FIG. 6 and FIG. 7.

[0027] Referring to FIG. 6, the substrate (10) where the trench (21) isformed is thermally oxidized in a furnace to form silicon thermal oxidewithout fluorine. In other words, a sidewall thermal oxide layer (23′)is formed inside the trench (21).

[0028] Referring to FIG. 6 and FIG. 7, the sidewall thermal oxide layer(23′) on the sidewall inside the trench is annealed in a process whichadditionally supplies a fluorine containing gas, such as NF₃ gas.Fluorine, dissociated from the fluorine containing gas, will diffusethrough the sidewall thermal oxide layer (23′) and be supplied to theinterface boundary between the sidewall thermal oxide layer (23′) andthe substrate (10). Dangling bonds are thereby reduced or removed andthe sidewall thermal oxide layer (23′) becomes the sidewall thermaloxide layer (23) containing fluorine by virtue of the diffusion processof fluorine.

[0029] The fluorine diffused to the interface boundary between thesubstrate of a trench and the thermal oxide may remove dangling bondsthrough two mechanisms. First, fluorine may be bonded to silicon atomshaving non-sharing electrons in the interface. Second, fluorine maysubstitute oxygen from Si—O bonds, and dissociated oxygen ions will formionic bonds with silicon atoms that have dangling bonds. Removal of thedangling bonds, which are a source of trapped charge in the interfaceboundary, may ameliorate current leakage problems of silicon devicesattributable to the dangling bonds. With regard to devicecharacteristics, removal of the dangling bonds may also prohibit leakagecurrent by inhibiting the penetration of impurities.

[0030] Preferred embodiments of the present invention have beendisclosed herein and, although specific terms are employed, they areused in a generic and descriptive sense only and not for the purpose oflimitation. Accordingly, it will be understood by those of ordinaryskill in the art that various changes in form and details may be madewithout departing from the spirit and scope of the invention as setforth in the following claims.

What is claimed is:
 1. A method for manufacturing a trench isolation ona silicon substrate, comprising: forming a trench area for deviceisolation in the silicon substrate, wherein the trench has innersidewalls; forming an oxide layer on a surface of the silicon substratethat forms the inner sidewalls of the trench; supplying healing elementsto the silicon substrate to remove dangling bonds; and filling thetrench with a device isolation layer.
 2. The method for manufacturing atrench isolation on a silicon substrate as claimed in claim 1, whereinthe healing elements are fluorine.
 3. The method for manufacturing atrench isolation on a silicon substrate as claimed in claim 1, whereinforming the oxide layer and supplying the healing elements are performedsimultaneously through thermal annealing in a fluorine and oxygen gasatmosphere.
 4. The method for manufacturing a trench isolation on asilicon substrate as claimed in claim 1, further comprising: forming asilicon nitride layer as an oxygen barrier layer after supplying thehealing elements to the silicon substrate and before filling the trenchwith the device isolation layer.
 5. The method for manufacturing atrench isolation on a silicon substrate as claimed in claim 1, whereinsupplying the healing elements is carried out by annealing the oxidelayer in a gas atmosphere containing the healing elements, after formingthe oxide layer on the surface of the substrate forming the innersidewalls of the trench.
 6. The method for manufacturing a trenchisolation on a silicon substrate as claimed in claim 1, whereinsupplying the healing elements comprises: forming an ion implantinglayer on the oxide layer; implanting the healing elements in the ionimplanting layer by an ion implantation; and diffusing the ion implantedhealing elements by means of a thermal annealing process.
 7. The methodfor manufacturing a trench isolation on a silicon substrate as claimedin claim 6, wherein the ion implanting layer is a polysilicon layer. 8.A semiconductor device with a trench isolation, comprising: a siliconsubstrate having a trench on a surface thereof; a filling layerpositioned in the trench for device isolation; and a silicon oxide layercontaining healing elements positioned between the filling layer and thesilicon substrate.
 9. The semiconductor device with a trench isolationas claimed in claim 8, wherein the healing elements are contained in aninterface boundary between the silicon oxide layer and the substrate.10. The semiconductor device with a trench isolation as claimed in claim8, further comprising a silicon nitride layer as an oxide barrier layerbetween the silicon oxide layer and the filling layer.
 11. Thesemiconductor device with a trench isolation as claimed in claim 8,wherein the filling layer comprises a spin-on-glass layer or a CVDlayer.
 12. The method for manufacturing a trench isolation on a siliconsubstrate as claimed in claim 1, wherein forming the trench comprises:forming a trench etching mask; and etching the silicon substrate usingthe trench etching mask to form the trench in the silicon substrate. 13.The method for manufacturing a trench isolation on a silicon substrateas claimed in claim 12, wherein forming the trench etching maskcomprises: forming a pad oxide layer on the silicon substrate; formingan etching prevention or barrier layer on the pad oxide layer;patterning the trench etching mask using a photolithography process;etching through the pad oxide layer and the etching prevention orbarrier layer; and removing the photoresist pattern.
 14. The method formanufacturing a trench isolation on a silicon substrate as claimed inclaim 12, wherein the etching of the silicon substrate is accomplishedby an anisotropic etch.
 15. The method for manufacturing a trenchisolation on a silicon substrate as claimed in claim 12, furthercomprising forming sloped sidewalls inside the trench while etching thesilicon substrate.
 16. The method for manufacturing a trench isolationon a silicon substrate as claimed in claim 13, wherein the etchingprevention or barrier layer is a silicon nitride layer.
 17. The methodfor manufacturing a trench isolation on a silicon substrate as claimedin claim 16, wherein the silicon nitride layer is deposited by CVD. 18.The method for manufacturing a trench isolation on a silicon substrateas claimed in claim 15, further comprising thermally oxidizing thesidewalls inside the trench to form a sidewall thermal oxide layerinside the trench.
 19. The method for manufacturing a trench isolationon a silicon substrate as claimed in claim 18, wherein the thermaloxidation is conducted in a furnace or a rapid thermal process machineat approximately 700° C.
 20. The method for manufacturing a trenchisolation on a silicon substrate as claimed in claim 18, furthercomprising supplying fluorine gas or NF₃ containing fluorine during thethermal oxidation in order to allow the sidewall thermal oxide layer andthe silicon substrate inside the trench to contain fluorine therein. 21.The method for manufacturing a trench isolation on a silicon substrateas claimed in claim 18, further comprising depositing a silicon nitrideliner on the entire silicon substrate.
 22. The method for manufacturinga trench isolation on a silicon substrate as claimed in claim 21,wherein the silicon nitride liner is deposited by CVD.
 23. The methodfor manufacturing a trench isolation on a silicon substrate as claimedin claim 22, wherein the silicon nitride liner is deposited to athickness of approximately 100 Angstroms.
 24. The method formanufacturing a trench isolation on a silicon substrate as claimed inclaim 22, further comprising forming a device isolation layer on thesilicon nitride liner to fill the trench.
 25. The method formanufacturing a trench isolation on a silicon substrate as claimed inclaim 24, wherein the device isolation layer is a silicon oxide layer.26. The method for manufacturing a trench isolation on a siliconsubstrate as claimed in claim 24, wherein the device isolation layer isdeposited by CVD, (HDP) CVD or by a SOG process.
 27. The method formanufacturing a trench isolation on a silicon substrate as claimed inclaim 24, further comprising performing a chemical mechanical polishingto remove the device isolation layer outside of the trench area andexpose the trench etching mask.
 28. The method for manufacturing atrench isolation on a silicon substrate as claimed in claim 24, furthercomprising performing a wet etching process to etch the silicon nitridelayer.
 29. The method for manufacturing a trench isolation on a siliconsubstrate as claimed in claim 28, wherein the wet etching process is aphosphoric acid wet etching process.
 30. The method for manufacturing atrench isolation on a silicon substrate as claimed in claim 24, furthercomprising removing the pad oxide layer to form a trench deviceisolation layer.
 31. The method for manufacturing a trench isolation ona silicon substrate as claimed in claim 30, wherein the trench deviceisolation layer has about a same level of surface height as the siliconsubstrate